The operating requirements for integrated circuits employed in performing logic functions are becoming more stringent as the art of digital computers and data processing equipment advances. In particular, the time required for a circuit to perform a logic operation is a limiting factor in the data handling capability of computing apparatus. Problems are also encountered in providing integrated circuits which are sufficiently immune to noise, whether generated within or externally of the circuit. Logic circuits may also be restricted in their usefulness because of limited "fan-out". "Fan-out" is a measure of the number of succeeding logic circuits which can be operated from the output connection of the circuit.
Size is also a significant consideration in the high speed data processing art. A plurality of interconnected logic circuits has been designed for fabrication within a single chip or die of semiconductor material. However, integrated logic circuits have certain problems in addition to those common to logic circuits in general. The ability to dissipate power is limited, and this situation may result in restricting the circuit to low fan-out and/or large gate delays. Since all of the individual circuit elements (e.g. transistors, diodes, resistors etc.) are located on a single small piece of semiconductor material (i.e. a chip), there are wireability considerations which must be taken into account.
Various types of digital logic circuits have been developed for fabrication as integrated circuits. Of these, the so-called transistor-transistor logic type (TTL) has become widely accepted because of the availability of certain circuits having favorable switching speeds, power dissipation, immunity to noise, fan-out, and capacitive load driving capability. The TTL technology is well known in the art. A sizeable number of patents, publications and texts disclose and discuss the design of TTL circuits. Reference is made, for example, to the texts:
(1) "Designing with TTL Integrated Circuits" by R. L. Morris and J. R. Miller, McGraw Hill, New York, N.Y., Copyright 1971; and PA1 (2) "Digital Integrated Electronics" by Herbert Taub and Donald Schilling, McGraw Hill, New York, N.Y., Copyright 1977. PA1 "Circuit Biasing Techniques" by J. B. Atkins, Vol. 8, No. 9, February 1966, page 1293. "Emitter-Follower Current Switch With In-Phase Feedback" by K. F. Mathews, Vol. 9, No. 3, August 1966 pages 322-4. "Unsaturated Transistor Logic Gate" by S. Wiedmann, Vol. 12, No. 11, April 1970, pages 2010-11. "Antisaturation Circuit" by J. A. Palmieri, Vol. 13, No. 2, July 1970, page 428. "Circuit With Negative Feedback" by L. C. Wu, Vol. 13, No. 2, July 1970, page 435. "Antisaturation TTL Circuit" by H. D. Varadarojan, Vol. 14, No. 1, June 1971, page 335. "Speed Up of TTL Circuits" by J. E. Gersbach, Vol. 14, No. 6, November 1971, page 1685. "Low Voltage T.sup.2 L Circuit by K. P. Johnson et al, Vol. 14, No. 10, March 1972, page 2859-0. "Low-Input Leakage T.sup.2 L Circuit by E. F. Culican, Vol. 14, No. 12, May 1972, pages 3681-2. "Transistor-Transistor Logic Circuit" by H. H. Berger et al, Vol. 16, No. 8, January 1974, pages 2643. "Microwatt TTL Circuits" by S. J. Aohi et al, Vol. 16, No. 10, March 1974, page 3273. "High-Input Impedance TTL Receiver Circuit" by R. F. Sechler, Vol. 18, No. 12, May 1976, pages 4088-0. "Constant-Current TTL Circuit" by W. Change et al, Vol. 19, No. 4, September 1976, page 1234. "Push-Pull T.sup.2 L Internal Circuit" by A. H. Dansky, Vol. 23, No. 4, September 1980, pages 1431-2. "N-Way AND Circuit and Multiplex Circuit for T.sup.2 L Family" by H. Beranger, Vol. 25, No. 1, June 1982, pages 334-5.
The patents and publications fully identified hereinafter disclose TTL type circuitry. These patents and publications do not constitute all of the patents and publications directed to TTL circuits, nor are they represented to include the most pertinent prior art to the invention disclosed hereinafter.
U.S. Pat. No. 3,229,119 entitled "Transistor Logic Circuits" granted Jan. 11, 1966 to R. E. Bohn et al. U.S. Pat. No. 3,283,170 entitled "Coupling Transistor Logic and Other Circuits" granted Nov. 1, 1966 to J. L. Buie. U.S. Pat. No. 3,473,047 entitled "High Speed Digital Logic Circuit Having Non-Saturating Output Transistor" granted Oct. 14, 1969 to R. E. Bohn et al. U.S. Pat. No. 3,524,992 entitled "Transistor Logic Circuit" granted Aug. 18, 1970 to J. J. Kardash. U.S. Pat. No. 3,555,294 entitled "Transistor--Transistor Logic Circuits Having Improved Voltage Transfer Characteristic" granted Jan. 12, 1971 to R. L. Treadway. U.S. Pat. No. 3,571,616 entitled "Logic Circuit" granted Mar. 23, 1971 to J. R. Andrews. U.S. Pat. No. 3,629,609 entitled "TTL Input Array with Bypass Diode" granted Dec. 21, 1971 to R. A. Pedersen. U.S. Pat. No. 3,693,032 entitled "Antisaturation Technique for TTL Circuits" granted Sept. 19, 1972 to J. R. Winnard. U.S. Pat. No. 3,934,157 entitled "TTL Circuit" granted Jan. 20, 1976 to W. J. Evans. U.S. Pat. No. 3,962,590 entitled "TTL Compatible Logic Gate Circuit" granted June 8, 1976 to J. Kane et al. U.S. Pat. No. 3,999,080 entitled "Transistor Coupled Logic Circuit" granted Dec. 21, 1976 to S. Weatherby Jr. et al. U.S. Pat. No. 4,049,975 entitled "Transistor Circuit" granted Sept. 20, 1977 to S. F. Colaco. U.S. Pat. No. 4,069,428 entitled "Transistor-Transistor-Logic Circuit" granted Jan. 17, 1978 to D. C. Reedy. U.S. Pat. No. 4,287,433 entitled "Transistor Logic Tristate Output With Reduced Power Dissipation" granted Sept. 1, 1981 to S. N. Goodspeed. U.S. Pat. No. 4,321,490 entitled "Transistor Logic Output For Reduced Power Consumption and Increased Speed During Low to High Transition" granted Mar. 23, 1982 to R. W. Bechdolt.
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